Processor Configuration Registers
MDA Present (MDAP): This bit works with the VGA Enable bit in the BCTRL register of
Device 1 to control the routing of processor initiated transactions targeting MDA
compatible I/O and memory address ranges. This bit should not be set when the VGA
Enable bit is not set. If the VGA enable bit is set, accesses to I/O address range x3BCh–
x3BFh are forwarded to DMI Interface. If the VGA enable bit is not set, accesses to I/O
address range x3BCh–x3BFh are treated just like any other I/O accesses – that is, the
cycles are forwarded to PCI Express if the address is within IOBASE and IOLIMIT and
ISA enable bit is not set; otherwise, they are forwarded to DMI Interface. MDA
resources are defined as the following:
Memory: 0B0000h–0B7FFFh
I/O:
3B4h, 3B5h, 3B8h, 3B9h, 3BAh, 3BFh,
(Including ISA address aliases, A[15:10] are not used in decode)
Any I/O reference that includes the I/O locations listed above, or their aliases, will be
forwarded to DMI Interface even if the reference includes I/O locations not listed
above.
For I/O reads which are split into multiple DWord accesses, this decode applies to each
DWord independently. For example, a read to x3B3 and x3B4 (quadword read to x3B0
with BE#=E7h) will result in a DWord read from PEG at 3B0 (BE#=Eh), and a DWord
read from DMI at 3B4 (BE=7h). Since the processor will not issue I/O writes crossing
the DWord boundary, this special case does not exist for writes.
Summary of decode priority:
1. Internal Graphics VGA, if enabled, gets:
03C0h–03CFh: always
03B0h–03BBh: if MSR[0]=0 (MSR is I/O register 03C2)
03D0h–03DFh: if MSR[0]=1
Note: 03BCh–03BFh never decodes to IGD; 3BCh–3BEh are parallel port I/Os, and
3BF is only used by true MDA devices, apparently.
2. Else, If MDA Present (if VGA on PEG is enabled), DMI gets:
x3B4,5,8,9,A,F (any access with any of these bytes enabled, regardless of the
other BEs)
3. Else, If VGA on PEG is enabled, PEG gets:
x3B0h–x3BBh
x3C0h–x3CFh
x3D0h–x3DFh
4. Else, if ISA Enable=1, DMI gets:
upper 768 bytes of each 1K block
5. Else, IOBASE/IOLIMIT apply
2.4
I/O Mapped Registers
The processor contains two registers that reside in the processor I/O address space –
the Configuration Address (CONFIG_ADDRESS) Register and the Configuration Data
(CONFIG_DATA) Register. The Configuration Address Register enables/disables the
configuration space and determines what portion of configuration space is visible
through the Configuration Data window.
46
Datasheet, Volume 2
INTEL [ INTEL ]
