Processor Configuration Registers
For regions mapped outside of the IGD (or if IGD is disabled), the legacy VGA memory
range A0000h–BFFFFh are mapped either to the DMI Interface or PCI Express
depending on the programming of the VGA Enable bit in the BCTRL configuration
register in the PEG configuration space, and the MDAPxx bits in the Legacy Access
Control (LAC) register in Device 0 configuration space. The same register controls
mapping VGA I/O address ranges. VGA I/O range is defined as addresses where A[9:0]
are in the ranges 3B0h to 3BBh and 3C0h to 3DFh (inclusive of ISA address aliases –
A[15:10] are not decoded). The function and interaction of these two bits is described
below:
VGA Enable: Controls the routing of processor initiated transactions targeting VGA
compatible I/O and memory address ranges. When this bit is set, the following
processor accesses will be forwarded to the PCI Express:
• memory accesses in the range 0A0000h to 0BFFFFh
• I/O addresses where A[9:0] are in the ranges 3B0h to 3BBh and 3C0h to 3DFh
(including ISA address aliases – A[15:10] are not decoded)
When this bit is set to a “1”:
• Forwarding of these accesses issued by the processor is independent of the I/O
address and memory address ranges defined by the previously defined base and
limit registers.
• Forwarding of these accesses is also independent of the settings of the ISA Enable
settings if this bit is “1”.
• Accesses to I/O address range x3BCh–x3BFh are forwarded to DMI Interface.
When this bit is set to a “0”:
• Accesses to I/O address range x3BCh–x3BFh are treated just like any other I/O
accesses – that is, the cycles are forwarded to PCI Express if the address is within
IOBASE and IOLIMIT and ISA enable bit is not set; otherwise, they are forwarded
to DMI Interface.
• VGA compatible memory and I/O range accesses are not forwarded to PCI Express
but rather they are mapped to DMI Interface unless they are mapped to PCI
Express using I/O and memory range registers defined above (IOBASE, IOLIMIT)
Table 2-7 shows the behavior for all combinations of MDA and VGA.
Table 2-7.
VGA and MDA I/O Transaction Mapping
VGA_en
MDAP
Range
Destination
Exceptions/Notes
0
0
1
1
1
0
1
0
1
1
VGA, MDA
Illegal
VGA
DMI Interface
Undefined behavior results
PCI Express
PCI Express
DMI Interface
VGA
MDA
Note: x3BCh–x3BEh will also go to DMI Interface
The same registers control mapping of VGA I/O address ranges. VGA I/O range is
defined as addresses where A[9:0] are in the ranges 3B0h to 3BBh and 3C0h to 3DFh
(inclusive of ISA address aliases – A[15:10] are not decoded). The function and
interaction of these two bits is described below.
Datasheet, Volume 2
45
INTEL [ INTEL ]
