Processor Configuration Registers
Figure 2-8. PEG Upstream VC0 Memory Map
Upstream Initiated VC0 Cycle Memory Map
2 TB
TOM = total physical DRAM
64 GB
REMAPLIMIT
TOUUD
REMAPBASE
4 GB
FEE0_0000h – FEEF_FFFFh( MSI)
GMADR
TOLUD
TSEG_BASE
TOLUD – (Gfx Stolen) – (Gfx GTT stolen)
(TSEG)
TSEG_BASE – DPR
A0000h–BFFFFh (VGA)
mem writes peer write (if matching PEG range else invalid)
mem reads Invalid transaction
mem writes Route based on SNR bit.
mem reads Route based on SNR bit.
mem writes CPU (IntLogical/IntPhysical)
mem reads Invalid transaction
mem writes non-snoop mem write
mem reads invalid transaction
mem writes invalid transaction
mem reads Invalid transaction
2.3.13.3
Legacy VGA and I/O Range Decode Rules
The legacy 128 KB VGA memory range 000A_0000h–000B_FFFFh can be mapped to
IGD (Device 2), PCI Express (Device 1 Functions or Device 6), and/or to the DMI
Interface depending on the programming of the VGA steering bits. Priority for VGA
mapping is constant in that the processor always decodes internally mapped devices
first. Internal to the processor, decode precedence is always given to IGD. The
processor always positively decodes internally mapped devices, namely the IGD.
Subsequent decoding of regions mapped to either PCI Express port or the DMI
Interface depends on the Legacy VGA configurations bits (VGA Enable & MDAP).
For the remainder of this section, PCI Express can refer to either the Device 1 port
functions or the Device 6 port.
VGA range accesses will always be mapped as UC type memory.
Datasheet, Volume 2
43
INTEL [ INTEL ]
