欢迎访问ic37.com |
会员登录 免费注册
发布采购

326769-002 参数 Datasheet PDF下载

326769-002图片预览
型号: 326769-002
PDF下载: 下载PDF文件 查看货源
内容描述: 移动第三代英特尔®科雷亚?? ¢处理器家族 [Mobile 3rd Generation Intel® Core™ Processor Family]
分类和应用:
文件页数/大小: 342 页 / 2513 K
品牌: INTEL [ INTEL ]
 浏览型号326769-002的Datasheet PDF文件第38页浏览型号326769-002的Datasheet PDF文件第39页浏览型号326769-002的Datasheet PDF文件第40页浏览型号326769-002的Datasheet PDF文件第41页浏览型号326769-002的Datasheet PDF文件第43页浏览型号326769-002的Datasheet PDF文件第44页浏览型号326769-002的Datasheet PDF文件第45页浏览型号326769-002的Datasheet PDF文件第46页  
Processor Configuration Registers  
2.3.13.2  
PCI Express* Interface Decode Rules  
All “SNOOP semantic” PCI Express transactions are kept coherent with processor  
caches.  
All “Snoop not required semantic” cycles must reference the direct DRAM address  
range. PCI Express non-snoop initiated cycles are not snooped.  
If a “Snoop not required semantic” cycle is outside of the address range mapped to  
system memory, then it will proceed as follows:  
• Reads: Sent to DRAM address 000C_0000h (non-snooped) and will return  
“unsuccessful completion.  
• Writes: Sent to DRAM address 000C_0000h (non-snooped) with byte enables all  
disabled Peer writes from PEG to DMI are not supported.  
If PEG bus master enable is not set, all reads and writes are treated as unsupported  
requests.  
2.3.13.2.1  
TC/VC Mapping Details  
1. VC0 (enabled by default)  
a. Snoop port and Non-snoop Asynchronous transactions are supported.  
b. Internal Graphics GMADR writes can occur. These will NOT be snooped  
regardless of the snoop not required (SNR) bit.  
c. Internal Graphics GMADR reads (unsupported).  
d. Peer writes are only supported between PEG ports. PEG to DMI peer write  
accesses are NOT supported.  
e. MSI can occur. These will route to the cores (IntLogical/IntPhysical) regardless  
of the SNR bit.  
2. VC1 is not supported  
3. VCm is not supported  
42  
Datasheet, Volume 2