Processor Configuration Registers
e. Internal Graphics GMADR writes and GMADR reads are not supported.
4. VCm accesses
a. See DMI2 specification for TC mapping to VCm. VCm access only map to Intel
ME stolen DRAM. These transactions carry the direct physical DRAM address (no
redirection or remapping of any kind will occur). This is how the PCH Intel
Management Engine accesses its dedicated DRAM stolen space.
b. DMI block will decode these transactions to ensure only Intel ME stolen memory
is targeted, and abort otherwise.
c. VCm transactions will only route non-snoop.
d. VCm transactions will not go through VTd remap tables.
e. The remapbase/remaplimit registers to not apply to VCm transactions.
Figure 2-7. Example: DMI Upstream VC0 Memory Map
Upstream Initiated VC0 Cycle Memory Map
2 TB
TOM = total physical DRAM
64 GB
REMAPLIMIT
TOUUD
REMAPBASE
4 GB
FEE0_0000h – FEEF_FFFFh( MSI)
GMADR
TOLUD
TSEG_BASE
TOLUD – (Gfx Stolen) – (Gfx GTT stolen)
(TSEG)
TSEG_BASE – DPR
A0000h–BFFFFh (VGA)
mem writes peer write (if matching PEG range else invalid)
mem reads Invalid transaction
mem writes Route based on SNR bit.
mem reads Route based on SNR bit.
mem writes CPU (IntLogical/IntPhysical)
mem reads Invalid transaction
mem writes non-snoop mem write
mem reads invalid transaction
mem writes peer write (based on Dev1 VGA en) else invalid
mem reads Invalid transaction
Datasheet, Volume 2
41
INTEL [ INTEL ]
