Processor Configuration Registers
2.21.19 IQH_REG—Invalidation Queue Head Register
This register indicates the invalidation queue head. This register is treated as RsvdZ by
implementations reporting Queued Invalidation (QI) as not supported in the Extended
Capability register.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
0/0/0/VC0PREMAP
80–87h
0000000000000000h
RO-V
64 bits
0000000000000h
Size:
BIOS Optimal Default
Reset
Value
RST/
PWR
Bit
Access
Description
63:19
RO
0h
0000h
0h
Reserved (RSVD)
Queue Head (QH)
This field specifies the offset (128-bit aligned) to the invalidation
queue for the command that will be fetched next by hardware.
Hardware resets this field to 0 whenever the queued invalidation
is disabled (QIES field Clear in the Global Status register).
18:4
3:0
RO-V
RO
Uncore
Reserved (RSVD)
2.21.20 IQT_REG—Invalidation Queue Tail Register
This register indicates the invalidation tail head. This register is treated as RsvdZ by
implementations reporting Queued Invalidation (QI) as not supported in the Extended
Capability register.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
0/0/0/VC0PREMAP
88–8Fh
0000000000000000h
RW-L
64 bits
0000000000000h
Size:
BIOS Optimal Default
Reset
Value
RST/
PWR
Bit
Access
Description
63:19
RO
0h
0000h
0h
Reserved (RSVD)
Queue Tail (QT)
This field specifies the offset (128-bit aligned) to the invalidation
queue for the command that will be written next by software.
18:4
3:0
RW-L
RO
Uncore
Reserved (RSVD)
334
Datasheet, Volume 2
INTEL [ INTEL ]
