Processor Configuration Registers
2.21.25 IEADDR_REG—Invalidation Event Address Register
This register specifies the Invalidation Event Interrupt message address.
This register is treated as RsvdZ by implementations reporting Queued Invalidation
(QI) as not supported in the Extended Capability register.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
0/0/0/VC0PREMAP
A8–ABh
00000000h
RW-L
32 bits
0h
Size:
BIOS Optimal Default
Reset
Value
RST/
PWR
Bit
Access
Description
Message address (MA)
When fault events are enabled, the contents of this register
specify the DWord-aligned address (bits 31:2) for the interrupt
request.
31:2
1:0
RW-L
RO
00000000h
0h
Uncore
Reserved (RSVD)
2.21.26 IEUADDR_REG—Invalidation Event Upper Address
Register
This register specifies the Invalidation Event interrupt message upper address.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
0/0/0/VC0PREMAP
AC–AFh
00000000h
RW-L
Size:
32 bits
Reset
Value
RST/
PWR
Bit
Access
Description
Message Upper Address (MUA)
Hardware implementations supporting Queued Invalidations and
Extended Interrupt Mode are required to implement this register.
31:0
RW-L
00000000h
Uncore
Hardware implementations not supporting Queued Invalidations
or Extended Interrupt Mode may treat this field as RsvdZ.
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Datasheet, Volume 2
INTEL [ INTEL ]
