Processor Configuration Registers
2.21.15 PLMBASE_REG—Protected Low-Memory Base Register
This register sets up the base address of DMA-protected low-memory region below
4 GB. This register must be set up before enabling protected memory through
PMEN_REG, and must not be updated when protected memory regions are enabled.
This register is always treated as RO for implementations not supporting protected low
memory region (PLMR field reported as Clear in the Capability register).
The alignment of the protected low memory region base depends on the number of
reserved bits (N:0) of this register. Software may determine N by writing all 1s to this
register, and finding the most significant zero bit position with 0 in the value read back
from the register. Bits N:0 of this register is decoded by hardware as all 0s.
Software must set up the protected low memory region below 4 GB.
Software must not modify this register when protected memory regions are enabled
(PRS field set in PMEN_REG).
B/D/F/Type:
Address Offset:
Reset Value:
Access:
0/0/0/VC0PREMAP
68–6Bh
00000000h
RW
32 bits
00000h
Size:
BIOS Optimal Default
Reset
Value
RST/
PWR
Bit
Access
Description
Protected Low-Memory Base (PLMB)
31:20
19:0
RW
RO
000h
0h
Uncore
This register specifies the base of protected low-memory region
in system memory.
Reserved (RSVD)
330
Datasheet, Volume 2
INTEL [ INTEL ]
