Processor Configuration Registers
2.21.22 ICS_REG—Invalidation Completion Status Register
This register reports completion status of invalidation wait descriptor with Interrupt
Flag (IF) set.
This register is treated as RsvdZ by implementations reporting Queued Invalidation
(QI) as not supported in the Extended Capability register.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
0/0/0/VC0PREMAP
9C–9Fh
00000000h
RW1CS
32 bits
Size:
BIOS Optimal Default
00000000h
Reset
Value
RST/
PWR
Bit
Access
Description
31:1
RO
0h
Reserved (RSVD)
Invalidation Wait Descriptor Complete (IWC)
This bit indicates completion of Invalidation Wait Descriptor
with Interrupt Flag (IF) field set. Hardware implementations
not supporting queued invalidations implement this field as
RsvdZ.
0
RW1CS
0b
Powergood
2.21.23 IECTL_REG—Invalidation Event Control Register
This register specifies the invalidation event interrupt control bits.
This register is treated as RsvdZ by implementations reporting Queued Invalidation
(QI) as not supported in the Extended Capability register.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
0/0/0/VC0PREMAP
A0–A3h
80000000h
RW-L, RO-V
32 bits
Size:
BIOS Optimal Default
00000000h
Reset
Value
RST/
PWR
Bit
Access
Description
Interrupt Mask (IM)
0 = No masking of interrupt. When an invalidation event
condition is detected, hardware issues an interrupt message
(using the Invalidation Event Data and Invalidation Event
Address register values).
31
RW-L
1b
Uncore
1 = This is the value on reset. Software may mask interrupt
message generation by setting this field. Hardware is
prohibited from sending the interrupt message when this
field is set.
336
Datasheet, Volume 2
INTEL [ INTEL ]
