Processor Configuration Registers
2.21.16 PLMLIMIT_REG—Protected Low-Memory Limit Register
This register sets up the limit address of DMA-protected low-memory region below
4 GB. This register must be set up before enabling protected memory through
PMEN_REG, and must not be updated when protected memory regions are enabled.
This register is always treated as RO for implementations not supporting protected low
memory region (PLMR field reported as Clear in the Capability register).
The alignment of the protected low memory region limit depends on the number of
reserved bits (N:0) of this register. Software may determine N by writing all 1s to this
register, and finding most significant zero bit position with 0 in the value read back
from the register. Bits N:0 of the limit register is decoded by hardware as all 1s.
The Protected low-memory base and limit registers functions as follows:
• Programming the protected low-memory base and limit registers with the same
value in bits 31:(N+1) specifies a protected low-memory region of size 2^(N+1)
bytes.
• Programming the protected low-memory limit register with a value less than the
Protected low-memory base register disables the protected low-memory region.
Software must not modify this register when protected memory regions are enabled
(PRS field set in PMEN_REG).
B/D/F/Type:
Address Offset:
Reset Value:
Access:
0/0/0/VC0PREMAP
6C–6Fh
00000000h
RW
32 bits
Size:
BIOS Optimal Default
00000h
Reset
Value
RST/
PWR
Bit
Access
Description
Protected Low-Memory Limit (PLML)
31:20
19:0
RW
RO
000h
0h
Uncore
This register specifies the last host physical address of the DMA-
protected low-memory region in system memory.
Reserved (RSVD)
Datasheet, Volume 2
331
INTEL [ INTEL ]
