Processor Configuration Registers
2.21.18 PHMLIMIT_REG—Protected High-Memory Limit Register
This register sets up the limit address of DMA-protected high-memory region. This
register must be set up before enabling protected memory through PMEN_REG, and
must not be updated when protected memory regions are enabled.
This register is always treated as RO for implementations not supporting protected high
memory region (PHMR field reported as Clear in the Capability register).
The alignment of the protected high memory region limit depends on the number of
reserved bits (N:0) of this register. Software may determine the value of N by writing
all 1s to this register, and finding most significant zero bit position below host address
width (HAW) in the value read back from the register. Bits N:0 of the limit register is
decoded by hardware as all 1s.
The protected high-memory base and limit registers functions as follows.
• Programming the protected low-memory base and limit registers with the same
value in bits HAW:(N+1) specifies a protected low-memory region of size 2^(N+1)
bytes.
• Programming the protected high-memory limit register with a value less than the
protected high-memory base register disables the protected high-memory region.
Software must not modify this register when protected memory regions are enabled
(PRS field set in PMEN_REG).
B/D/F/Type:
Address Offset:
Reset Value:
Access:
0/0/0/VC0PREMAP
78–7Fh
0000000000000000h
RW
64 bits
000000000000h
Size:
BIOS Optimal Default
Reset
Value
RST/
PWR
Bit
Access
Description
63:39
RO
0h
00000h
0h
Reserved (RSVD)
Protected High-Memory Limit (PHML)
This register specifies the last host physical address of the DMA-
protected high-memory region in system memory.
Hardware ignores and does not implement bits 63:HAW, where
HAW is the host address width.
38:20
19:0
RW
RO
Uncore
Reserved (RSVD)
Datasheet, Volume 2
333
INTEL [ INTEL ]
