Processor Configuration Registers
2.21.17 PHMBASE_REG—Protected High-Memory Base Register
This register sets up the base address of DMA-protected high-memory region. This
register must be set up before enabling protected memory through PMEN_REG, and
must not be updated when protected memory regions are enabled.
This register is always treated as RO for implementations not supporting protected high
memory region (PHMR field reported as Clear in the Capability register).
The alignment of the protected high memory region base depends on the number of
reserved bits (N:0) of this register. Software may determine N by writing all 1s to this
register, and finding most significant zero bit position below host address width (HAW)
in the value read back from the register. Bits N:0 of this register are decoded by
hardware as all 0s.
Software may set up the protected high memory region either above or below 4 GB.
Software must not modify this register when protected memory regions are enabled
(PRS field set in PMEN_REG).
B/D/F/Type:
Address Offset:
Reset Value:
Access:
0/0/0/VC0PREMAP
70–77h
0000000000000000h
RW
64 bits
Size:
BIOS Optimal Default
000000000000h
Reset
Value
RST/
PWR
Bit
Access
Description
63:39
RO
0h
00000h
0h
Reserved (RSVD)
Protected High-Memory Base (PHMB)
This register specifies the base of protected (high) memory
region in system memory.
Hardware ignores, and does not implement, bits 63:HAW, where
HAW is the host address width.
38:20
19:0
RW
RO
Uncore
Reserved (RSVD)
332
Datasheet, Volume 2
INTEL [ INTEL ]
