Processor Configuration Registers
2.21.13 AFLOG_REG—Advanced Fault Log Register
This register specifies the base address of the memory-resident fault-log region. This
register is treated as RsvdZ for implementations not supporting advanced translation
fault logging (AFL field reported as 0 in the Capability register).
B/D/F/Type:
Address Offset:
Reset Value:
Access:
0/0/0/VC0PREMAP
58–5Fh
0000000000000000h
RO
64 bits
000h
Size:
BIOS Optimal Default
Reset
Value
RST/
PWR
Bit
Access
Description
Fault Log Address (FLA)
This field specifies the base of 4 KB aligned fault-log region in
system memory. Hardware ignores and does not implement bits
63:HAW, where HAW is the host address width.
Software specifies the base address and size of the fault log
region through this register, and programs it in hardware through
the SFL field in the Global Command register. When
implemented, reads of this field return the value that was last
programmed to it.
00000000
00000h
63:12
RO
Uncore
Uncore
Fault Log Size (FLS)
This field specifies the size of the fault log region pointed by the
FLA field. The size of the fault log region is 2^X * 4KB, where X is
the value programmed in this register.
When implemented, reads of this field return the value that was
last programmed to it.
11:9
8:0
RO
RO
0h
0h
Reserved (RSVD)
328
Datasheet, Volume 2
INTEL [ INTEL ]
