Processor Configuration Registers
2.21.10 FEDATA_REG—Fault Event Data Register
This register specifies the interrupt message data.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
0/0/0/VC0PREMAP
3C–3Fh
00000000h
RW
32 bits
Size:
Reset
Value
RST/
PWR
Bit
Access
RW
Description
Extended Interrupt Message Data (EIMD):
This field is valid only for implementations supporting 32-bit
interrupt data fields.
Hardware implementations supporting only 16-bit interrupt data
may treat this field as RsvdZ.
31:16
15:0
0000h
0000h
Uncore
Uncore
Interrupt Message Data (IMD):
Data value in the interrupt request.
RW
2.21.11 FEADDR_REG—Fault Event Address Register
This register specifies the interrupt message address.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
0/0/0/VC0PREMAP
40–43h
00000000h
RW
32 bits
0h
Size:
BIOS Optimal Default
Reset
Value
RST/
PWR
Bit
Access
Description
Message Address (MA)
00000000
h
When fault events are enabled, the contents of this register
specify the DWord-aligned address (bits 31:2) for the interrupt
request.
31:2
1:0
RW
RO
Uncore
0h
Reserved (RSVD)
2.21.12 FEUADDR_REG—Fault Event Upper Address Register
This register specifies the interrupt message upper address.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
0/0/0/VC0PREMAP
44–47h
00000000h
RW
Size:
32 bits
Reset
Value
RST/
PWR
Bit
Access
Description
Message upper address (MUA)
Hardware implementations supporting Extended Interrupt Mode
are required to implement this register.
31:0
RW
00000000h
Uncore
Hardware implementations not supporting Extended Interrupt
Mode may treat this field as RsvdZ.
Datasheet, Volume 2
327
INTEL [ INTEL ]
