Processor Configuration Registers
2.14.5
TC_RFP_C1—Refresh Parameters Register
This register provides refresh parameters.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
0/0/0/MCHBAR MC1
4694–4697h
0000980Fh
RW-L
Size:
32 bits
BIOS Optimal Default
0000h
Reset
Value
RST/
PWR
Bit
Access
Description
31:18
RO
0h
Reserved (RSVD)
Double Refresh Control (DOUBLE_REFRESH_CONTROL)
This field will allow the double self refresh enable/disable.
00 = Double refresh rate when DRAM is WARM/HOT.
01 = Force double self refresh regardless of temperature.
10 = Disable double self refresh regardless of temperature.
11 = Reserved
17:16
15:12
RW-L
RW-L
00b
Uncore
Uncore
Refresh panic WM (Refresh_panic_wm)
tREFI count level in which the refresh priority is panic (default is
9)
9h
It is recommended to set the panic WM at least to 9, in order to
use the maximum no-refresh period possible
Refresh high priority WM (Refresh_HP_WM)
11:8
7:0
RW-L
RW-L
8h
Uncore
Uncore
tREFI count level that turns the refresh priority to high (default is
8)
Rank idle timer for opportunistic refresh (OREF_RI)
Rank idle period that defines an opportunity for refresh, in DCLK
cycles
0Fh
Datasheet, Volume 2
249
INTEL [ INTEL ]
