Processor Configuration Registers
2.14.6
TC_RFTP_C1—Refresh Timing Parameters Register
Thie register provides refresh timing parameters.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
0/0/0/MCHBAR MC1
4698–469Bh
46B41004h
RW-L
Size:
32 bits
Reset
Value
RST/
PWR
Bit
Access
Description
9 * tREFI (tREFIx9)
Period of minimum between 9*tREFI and tRAS maximum
(normally 70 us) in 1024 * DCLK cycles (default is 35h) – need to
reduce 100 DCLK cycles – uncertainty on timing of panic refresh
31:25
RW-L
23h
Uncore
Refresh Execution Time (tRFC)
24:16
15:0
RW-L
RW-L
0B4h
Uncore
Uncore
Time of refresh – from beginning of refresh until next ACT or
refresh is allowed (in DCLK cycles, default is 180h)
tREFI Period in DCLK Cycles (tREFI)
Defines the average period between refreshes, and the rate that
tREFI counter is incremented (in DCLK cycles, default is 4100h)
1004h
2.14.7
TC_SRFTP_C1—Self refresh Timing Parameters Register
Thie register provides self-refresh timing parameters.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
0/0/0/MCHBAR MC1
46A4–46A7h
0100B200h
RW-L
Size:
32 bits
BIOS Optimal Default
0h
Reset
Value
RST/
PWR
Bit
Access
Description
(tMOD)
The time between MRS command and any other command in
DCLK cycles.
Actual value is 8 + programmed-Value. For example when
programming 4 in the field, tMOD value is actually 12 DCLK
cycles.
31:28
RW-L
0h
Uncore
27:26
25:16
RO
0h
Reserved (RSVD)
(tZQOPER)
RW-L
100h
Uncore
Uncore
This field defines the period required for ZQCL after SR exit.
(tXS_offset)
Delay from SR exit to the first DDR command.
tXS = tRFC+10ns. Setup of tXS_offset is # of cycles for 10 ns.
The range is between 3 and 11 DCLK cycles.
15:12
11:0
RW-L
RW-L
Bh
(tXSDLL)
Delay between DDR SR exit and the first command that requires
data RD/WR from DDR is in the range of 128 to 1024 DCLK
cycles, though all JEDEC DDRs assume 512 DCLK cycles.
200h
Uncore
250
Datasheet, Volume 2
INTEL [ INTEL ]
