Processor Configuration Registers
2.15
MCHBAR Registers in Memory Controller –
Integrated Memory Peripheral Hub (IMPH)
Table 2-18. MCHBAR Registers in Memory Controller –Integrated Memory Peripheral
Hub (IMPH) Register Address Map
Address
Offset
Register Symbol
Register Name
Reset Value
Access
0–740Bh
RSVD
CRDTCTL3
CRDTCTL4
RSVD
Reserved
—
—
740C–740Fh
7410–7413h
7410C–7FFFh
Credit Control 3
Credit Control 4
Reserved
B124F851h
00000017h
—
RW-L
RW-L
—
2.15.1
CRDTCTL3—Credit Control 3 Register
This register will have the minimum Read Return Tracker credits for each of the
PEG/DMI/GSA streams.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
0/0/0/MCHBAR IMPH
740C–740Fh
B124F851h
RW-L
Size:
32 bits
Reset
Value
RST/
PWR
Bit
Access
RW-L
RW-L
RW-L
RW-L
RW-L
RW-L
RW-L
RW-L
RW-L
RW-L
Description
GSA VC1 Minimum Completion Credits (GSAVC1)
Minimum number of credits for GSA VC1 completions
31:27
26:24
23:21
20:18
17:15
14:12
11:9
8:6
16h
1h
1h
1h
1h
7h
4h
1h
2h
1h
Uncore
Uncore
Uncore
Uncore
Uncore
Uncore
Uncore
Uncore
Uncore
Uncore
GSA VC0 Minimum Completion Credits (GSAVC0)
Minimum number of credits for GSA VC0 completions
PEG60 VC0 Minimum Completion Credits (PEG60VC0)
Minimum number of credits for PEG60 VC0 completions
PEG12 VC0 Minimum Completion Credits (PEG12VC0)
Minimum number of credits for PEG12 VC0 completions
PEG11 VC0 Minimum Completion Credits (PEG11VC0)
Minimum number of credits for PEG11 VC0 completions
PEG10 VC0 Minimum Completion Credits (PEG10VC0)
Minimum number of credits for PEG10 VC0 completions
DMI VC1 Minimum Completion Credits (DMIVC1)
Minimum number of credits for DMI VC1 completions
DMI VCm Minimum Completion Credits (DMIVCM)
Minimum number of credits for DMI VCm completions
DMI VCp Minimum Completion Credits (DMIVCP)
Minimum number of credits for DMI VCp completions
5:3
DMI VC0 Minimum Completion Credits (DMIVC0)
Minimum number of credits for DMI VC0 completions
2:0
Datasheet, Volume 2
251
INTEL [ INTEL ]
