Processor Configuration Registers
2.11.13 APICLIMIT—APIC Base Address Limit Register
B/D/F/Type:
Address Offset:
Reset Value:
Access:
0/6/0/MMR
244–247h
00000000h
RW
Size:
32 bits
BIOS Optimal Default
000000h
Reset
Value
RST/
PWR
Bit
Access
Description
31:12
RO
0h
00h
0h
Reserved (RSVD)
APIC Base Address (APICLIMIT):
Bits 19:12 of the APIC Limit
Bits 31:20 are assumed to be FECh. Bits 0:11 are don't care for
address decode.
Address decoding to the APIC range is done as:
11:4
3:0
RW
RO
Uncore
APIC_BASE [31:12] ≤ A[31:12] ≤ APIC_LIMIT[31:12]
Reserved (RSVD)
2.11.14 CMNRXERR—Common Rx Error Register
B/D/F/Type:
Address Offset:
Reset Value:
Access:
0/6/0/MMR
C34–C37h
00000000h
RW1CS
32 bits
0000000h
Size:
BIOS Optimal Default
Reset
Value
RST/
PWR
Bit
Access
Description
31:3
RO
0h
0b
0h
Reserved (RSVD)
Gen1/2 UFD Framing Error Status (UFDFRAMEERR):
Only applicable for Gen1/Gen2. When set, this field indicates
that a framing error occurred in the Link. (that is, dropped STP,
dropped SDP, dropped END)
2
RW1CS
RO
Powergood
1:0
Reserved (RSVD)
212
Datasheet, Volume 2
INTEL [ INTEL ]
