Processor Configuration Registers
2.11.6
VC0RSTS—VC0 Resource Status Register
This register reports the Virtual Channel specific status.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
0/6/0/MMR
11A–11Bh
0002h
RO-V
Size:
16 bits
BIOS Optimal Default
0000h
Reset
Value
RST/
PWR
Bit
Access
Description
15:2
RO
0h
1b
0h
Reserved (RSVD)
VC0 Negotiation Pending (VC0NP)
0 = The VC negotiation is complete.
1 = The VC resource is still in the process of negotiation
(initialization or disabling).
This bit indicates the status of the process of Flow Control
initialization. It is set by default on Reset, as well as whenever
the corresponding Virtual Channel is Disabled or the Link is in the
DL_Down state. It is cleared when the link successfully exits the
FC_INIT2 state.
Before using a Virtual Channel, software must check whether the
VC Negotiation Pending fields for that Virtual Channel are cleared
in both Components on a Link.
1
RO-V
Uncore
0
RO
Reserved (RSVD)
2.11.7
RCLDECH—Root Complex Link Declaration Enhanced
This capability declares links from this element (PEG) to other elements of the root
complex component to which it belongs. See PCI Express* specification for
link/topology declaration requirements.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
0/6/0/MMR
140–143h
00010005h
RO-V, RO
32 bits
Size:
Reset
Value
RST/
PWR
Bit
Access
Description
31:20
RO
0h
Reserved (RSVD)
Link Declaration Capability Version (LDCV)
Hardwired to 1 to indicate compliances with the 1.1 version of
the PCI Express specification.
Note: This version does not change for 2.0 compliance.
19:16
15:0
RO
RO
1h
Uncore
Extended Capability ID (ECID)
Value of 0005 h identifies this linked list item (capability
structure) as being for PCI Express Link Declaration Capability.
0005h
Uncore
See corresponding Egress Port Link Declaration Capability
registers for diagram of Link Declaration Topology.
208
Datasheet, Volume 2
INTEL [ INTEL ]
