Processor Configuration Registers
2.11.11 LE1AH—Link Entry 1 Address Register
This register provides the second part of a Link Entry that declares an internal link to
another Root Complex Element.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
0/6/0/MMR
15C–15Fh
00000000h
RW-O
32 bits
000000h
Size:
BIOS Optimal Default
Reset
Value
RST/
PWR
Bit
Access
Description
31:8
RO
0h
Reserved (RSVD)
Link Address (LA)
Memory mapped base address of the RCRB that is the target
element (Egress Port) for this link entry.
7:0
RW-O
00h
Uncore
BIOS Requirement: This field is inserted by BIOS such that it
matches PXPEPBAR.
2.11.12 APICBASE—APIC Base Address Register
B/D/F/Type:
Address Offset:
Reset Value:
Access:
0/6/0/MMR
240–243h
00000000h
RW
Size:
32 bits
BIOS Optimal Default
000000h
Reset
Value
RST/
PWR
Bit
Access
Description
31:12
RO
0h
Reserved (RSVD)
APIC Base Address (APICBASE):
Bits 19:12 of the APIC Base
Bits 31:20 are assumed to be FECh. Bits 0:11 are don't care for
address decode.
Address decoding to the APIC range is done as:
11:4
RW
00h
Uncore
Uncore
APIC_BASE [31:12] ≤ A[31:12] ≤ APIC_LIMIT[31:12]
3:1
0
RO
0h
0b
Reserved (RSVD)
APIC Range Enable (APICRE):
Enables the decode of the APIC window.
0 = Disable
RW
1 = Enable
Datasheet, Volume 2
211
INTEL [ INTEL ]
