Processor Configuration Registers
2.11.8
ESD—Element Self Description Register
This register provides information about the root complex element containing this Link
Declaration Capability.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
0/6/0/MMR
144–147h
05000100h
RO, RW-O
32 bits
Size:
BIOS Optimal Default
0h
Reset
Value
RST/
PWR
Bit
Access
Description
Port Number (PN)
Specifies the port number associated with this element with
respect to the component that contains this element.
Note the value is instantiation dependent:
BDF 0.1.0 --> 02
BDF 0.1.1 --> 03
BDF 0.1.2 --> 04
BDF 0.6.0 --> 05
31:24
RO
05h
Uncore
Uncore
Component ID (CID)
Identifies the physical component that contains this Root
Complex Element.
BIOS Requirement: This field must be initialized according to
guidelines in the PCI Express* Isochronous/Virtual Channel
Support Hardware Programming Specification (HPS).
23:16
15:8
RW-O
RO
00h
01h
Number of Link Entries (NLE)
Indicates the number of link entries following the Element Self
Description. This field reports 1 (to Egress port only).
Uncore
Uncore
7:4
3:0
RO
RO
0h
0h
Reserved (RSVD)
Element Type (ET)
Indicates Configuration Space Element.
Datasheet, Volume 2
209
INTEL [ INTEL ]
