Processor Configuration Registers
B/D/F/Type:
Address Offset:
Reset Value:
Access:
0/6/0/MMR
110–113h
00000001h
RO
Size:
32 bits
BIOS Optimal Default
00h
Reset
Value
RST/
PWR
Bit
Access
Description
Port Arbitration Capability (PAC)
Indicates types of Port Arbitration supported by the VC resource.
This field is valid for all Switch Ports, Root Ports that support
peer-to-peer traffic, and RCRBs, but not for PCI Express Endpoint
devices or Root Ports that do not support peer to peer traffic.
Each bit location within this field corresponds to a Port Arbitration
Capability defined below. When more than one bit in this field is
set, it indicates that the VC resource can be configured to provide
different arbitration services.
Software selects among these capabilities by writing to the Port
Arbitration Select field (see below).
Defined bit positions are:
7:0
RO
01h
Uncore
Bit 0
Non-configurable hardware-fixed arbitration scheme,
such as Round Robin (RR)
Bit 1
Weighted Round Robin (WRR) arbitration with 32
phases
Bit 2
Bit 3
Bit 4
Bit 5
WRR arbitration with 64 phases
WRR arbitration with 128 phases
Time-based WRR with 128 phases
WRR arbitration with 256 phases
Reserved
Bits 6-7
Processor only supported arbitration indicates "Non-configurable
hardware-fixed arbitration scheme".
206
Datasheet, Volume 2
INTEL [ INTEL ]
