Processor Configuration Registers
2.11.3
PVCCTL—Port VC Control Register
B/D/F/Type:
Address Offset:
Reset Value:
Access:
0/6/0/MMR
10C–10Dh
0000h
RW, RO
16 bits
000h
Size:
BIOS Optimal Default
Reset
Value
RST/
PWR
Bit
Access
Description
15:4
RO
0h
Reserved (RSVD)
VC Arbitration Select (VCAS)
This field will be programmed by software to the only possible
value as indicated in the VC Arbitration Capability field. Since
there is no other VC supported than the default, this field is
reserved.
3:1
0
RW
RO
000b
Uncore
Uncore
Reserved for Load VC Arbitration Table (VCARB)
Used for software to update the VC Arbitration Table when VC
arbitration uses the VC Arbitration Table. As a VC Arbitration
Table is never used by this component this field will never be
used.
0b
2.11.4
VC0RCAP—VC0 Resource Capability Register
B/D/F/Type:
Address Offset:
Reset Value:
Access:
0/6/0/MMR
110–113h
00000001h
RO
Size:
32 bits
BIOS Optimal Default
00h
Reset
Value
RST/
PWR
Bit
Access
Description
31:24
23
RO
RO
RO
00h
0h
Uncore
Reserved for Port Arbitration Table Offset (PATO)
Reserved (RSVD)
22:16
00h
Uncore
Reserved for Maximum Time Slots (MTS)
Reject Snoop Transactions (RSNPT)
0 = Transactions with or without the No Snoop bit set within the
TLP header are allowed on this VC.
1 = When set, any transaction for which the No Snoop attribute
is applicable but is not set within the TLP Header will be
rejected as an Unsupported Request
15
RO
RO
0b
0h
Uncore
14:8
Reserved (RSVD)
Datasheet, Volume 2
205
INTEL [ INTEL ]
