Processor Configuration Registers
2.10
PCI Device 6 Registers
Table 2-13. PCI Device 6 Register Address Map (Sheet 1 of 2)
Address
Offset
Register
Symbol
Register Name
Reset Value
Access
0–1h
2–3h
4–5h
VID
DID
Vendor Identification
8086h
015Dh
0000h
RO
Device Identification
PCI Command
PCI Status
RO-FW
RW, RO
PCICMD
RW1C, RO, RO-
V
6–7h
PCISTS
0010h
8h
9–Bh
Ch
RID
CC
Revision Identification
Class Code
00h
060400h
00h
RO-FW
RO
CL
Cache Line Size
RW
Dh
RSVD
Reserved
0h
RO
Eh
HDR
Header Type
81h
RO
Fh
RSVD
Reserved
0h
RO
18h
PBUSN
SBUSN
SUBUSN
RSVD
Primary Bus Number
Secondary Bus Number
Subordinate Bus Number
Reserved
00h
RO
19h
00h
RW
1Ah
00h
RW
1Bh
0h
RO
1Ch
IOBASE
IOLIMIT
SSTS
I/O Base Address
I/O Limit Address
Secondary Status
Memory Base Address
Memory Limit Address
Prefetchable Memory Base Address
Prefetchable Memory Limit Address
F0h
RW
1Dh
00h
RW
1E–1Fh
20–21h
22–23h
24–25h
26–27h
0000h
FFF0h
0000h
FFF1h
0001h
RW1C, RO
RW
MBASE
MLIMIT
PMBASE
PMLIMIT
RW
RW, RO
RW, RO
Prefetchable Memory Base Address
Upper
28–2Bh
2C–2Fh
PMBASEU
PMLIMITU
00000000h
00000000h
RW
RW
Prefetchable Memory Limit Address
Upper
30–33h
34h
RSVD
CAPPTR
RSVD
Reserved
0h
88h
RO
RO
Capabilities Pointer
Reserved
35–3Bh
3Ch
0h
RO
INTRLINE
INTRPIN
BCTRL
Interrupt Line
00h
RW
3Dh
Interrupt Pin
01h
RW-O, RO
RO, RW
RO
3E–3Fh
40–7Fh
80–83h
84–87h
Bridge Control
0000h
0h
RSVD
Reserved
PM_CAPID
PM_CS
Power Management Capabilities
Power Management Control/Status
C8039001h
00000008h
RO, RO-V
RO, RW
Subsystem ID and Vendor ID
Capabilities
88–8Bh
8C–8Fh
SS_CAPID
SS
0000800Dh
00008086h
RO
Subsystem ID and Subsystem Vendor
ID
RW-O
Datasheet, Volume 2
161
INTEL [ INTEL ]
