Processor Configuration Registers
2.8.14
SID2—Subsystem Identification Register
This register is used to uniquely identify the subsystem where the PCI device resides.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
0/2/0/PCI
2E–2Fh
0000h
RW-O
Size:
16 bits
Reset
Value
RST/
PWR
Bit
Access
Description
Subsystem Identification (SUBID)
This value is used to identify a particular subsystem. This field
should be programmed by BIOS during boot-up. Once written,
this register becomes Read-only. This register can only be cleared
by a Reset.
15:0
RW-O
0000h
Uncore
2.8.15
ROMADR—Video BIOS ROM Base Address Register
The IGD does not use a separate BIOS ROM; therefore this register is hardwired to 0s.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
0/2/0/PCI
30–33h
00000000h
RO
32 bits
000h
Size:
BIOS Optimal Default
Reset
Value
RST/
PWR
Bit
Access
Description
ROM Base Address (RBA)
31:18
RO
0000h
Uncore
Uncore
Hardwired to 0s.
Address Mask (ADMSK)
Hardwired to 0s to indicate 256 KB address range.
17:11
10:1
0
RO
RO
RO
00h
0h
Reserved (RSVD)
ROM BIOS Enable (RBE)
0 = ROM not accessible.
0b
Uncore
2.8.16
CAPPOINT—Capabilities Pointer Register
This register points to a linked list of capabilities implemented by this device.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
0/2/0/PCI
34h
90h
RO-V
8 bits
Size:
Reset
Value
RST/
PWR
Bit
Access
Description
Capabilities Pointer Value (CPV)
This field contains an offset into the function's PCI Configuration
Space for the first item in the New Capabilities Linked List, the
MSI Capabilities ID registers at address 90h or the Power
Management capability at D0h.
7:0
RO-V
90h
Uncore
This value is determined by the configuration in CAPL[0].
Datasheet, Volume 2
157
INTEL [ INTEL ]
