Processor Configuration Registers
2.10.2
DID—Device Identification Register
This register combined with the Vendor Identification register uniquely identifies any
PCI device.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
0/6/0/PCI
2–3h
015Dh
RO-FW
16 bits
Size:
Reset
Value
RST/
PWR
Bit
Access
Description
Device Identification Number MSB (DID_MSB)
15:0
RO-FW
015Dh
Uncore
Identifier assigned to the processor root port (virtual PCI-to-PCI
bridge, PCI Express Graphics port).
2.10.3
PCICMD—PCI Command Register
B/D/F/Type:
Address Offset:
Reset Value:
Access:
0/6/0/PCI
4–5h
0000h
RW, RO
16 bits
00h
Size:
BIOS Optimal Default
Reset
Value
RST/
PWR
Bit
Access
Description
15:11
RO
0h
Reserved (RSVD)
INTA Assertion Disable (INTAAD)
0 = This device is permitted to generate INTA interrupt
messages.
1 = This device is prevented from generating interrupt
messages. Any INTA emulation interrupts already asserted
must be de-asserted when this bit is set.
Only affects interrupts generated by the device (PCI INTA from a
PME or Hot-plug event) controlled by this command register. It
does not affect upstream MSIs, upstream PCI INTA-INTD assert
and deassert messages.
10
RW
RO
0b
Uncore
Uncore
Note: PCI Express* Hot-Plug is not supported on the processor.
Fast Back-to-Back Enable (FB2B)
Not Applicable or Implemented. Hardwired to 0.
9
0b
Datasheet, Volume 2
163
INTEL [ INTEL ]
