Processor Configuration Registers
2.6.47
DCTL2—Device Control 2 Register
B/D/F/Type:
Address Offset:
Reset Value:
Access:
0/1/0–2/PCI
C8–C9h
0000h
RW-V, RW
16 bits
0000h
Size:
BIOS Optimal Default
Reset
Value
RST/
PWR
Bit
Access
Description
15:12
RO
0h
Reserved (RSVD)
Latency Tolerance and BW Reporting Mechanism Enable
(LTREN)
When set to 1b, this bit enables the Latency Tolerance &
Bandwidth Requirement Reporting (LTBWR) mechanism.
This bit is required for all Functions that support the LTBWR
Capability. For a Multi-Function device associated with an
upstream port of a device that implements LTBWR, the bit in
Function 0 is of type RW, and only Function 0 controls the
component’s Link behavior. In all other Functions of that device,
this bit is of type RsvdP.
11
RW-V
0b
Uncore
Components that do not implement LTBWR are permitted to
hardwire this bit to 0b.
Reset Value of this bit is 0b.
This bit is cleared when the port goes to DL_down state.
Hardware ignores the value of this bit.
10:6
5
RO
RW
RO
0h
0b
0h
Reserved (RSVD)
ARI Forward Enable (ARIFEN)
When set, the Downstream Port disables its traditional Device
Number field being 0 enforcement when turning a Type 1
Configuration Request into a Type 0 Configuration Request,
permitting access to Extended Functions in an ARI Device
immediately below the Port.
Reset Value of this bit is 0b. It must be hardwired to 0b if the ARI
Forwarding Supported bit is 0b.
Uncore
4:0
Reserved (RSVD)
128
Datasheet, Volume 2
INTEL [ INTEL ]
