Processor Configuration Registers
B/D/F/Type:
Address Offset:
Reset Value:
Access:
0/1/0–2/PCI
BA–BBh
0000h
RO, RW1C, RO-V
16 bits
Size:
BIOS Optimal Default
00h
Reset
Value
RST/
PWR
Bit
Access
Description
Presence Detect Changed (PDC)
A pulse indication that the inband presence detect state has
changed.
This bit is set when the value reported in Presence Detect State is
changed.
3
RW1C
0b
0b
Uncore
Uncore
Reserved for MRL Sensor Changed (MSC)
If an MRL sensor is implemented, this bit is set when a MRL
Sensor state change is detected. If an MRL sensor is not
implemented, this bit must not be set.
2
1
0
RO
RO
RO
Reserved for Power Fault Detected (PFD)
If a Power Controller that supports power fault detection is
implemented, this bit is set when the Power Controller detects a
power fault at this slot. Depending on hardware capability, it is
possible that a power fault can be detected at any time,
independent of the Power Controller Control setting or the
occupancy of the slot. If power fault detection is not supported,
this bit must not be set.
0b
0b
Uncore
Uncore
Reserved for Attention Button Pressed (ABP)
If an Attention Button is implemented, this bit is set when the
attention button is pressed. If an Attention Button is not
supported, this bit must not be set.
124
Datasheet, Volume 2
INTEL [ INTEL ]
