Processor Configuration Registers
2.7
PCI Device 1 Function 0–2 Extended Configuration
Registers
Table 2-10. PCI Device 1 Function 0–2 Extended Configuration Register Address Map
Address
Offset
Register
Symbol
Register Name
Reset Value
Access
0–103h
RSVD
PVCCAP1
PVCCAP2
PVCCTL
Reserved
0h
RO
RO
104–107h
108–10Bh
10C–10Dh
10E–10Fh
110–113h
114–117h
118–119h
11A–11Bh
11C–207h
208–20Bh
20C–D9Fh
DA0–DA3h
DA4–DA7h
DA8–DABh
DAC–DAFh
DB0–DB3h
Port VC Capability Register 1
Port VC Capability Register 2
Port VC Control
00000000h
00000000h
0000h
RO
RW, RO
RO
RSVD
Reserved
0h
VC0RCAP
VC0RCTL
RSVD
VC0 Resource Capability
VC0 Resource Control
00000001h
800000FFh
0h
RO
RO, RW
RO
Reserved
VC0RSTS
RSVD
VC0 Resource Status
0002h
RO-V
RO
Reserved
0h
PEG_TC
RSVD
PCI Express Completion Time-out
Reserved
00010005h
02000100h
07080708h
07080708h
07080708h
07080708h
07080708h
RW
RO, RW-O
RW
EQCTL0_1
EQCTL2_3
EQCTL4_5
EQCTL6_7
EQCTL8_9
Lane 0/1 Equalization Control Register
Lane 2/3 Equalization Control Register
Lane 4/5 Equalization Control Register
Lane 6/7 Equalization Control Register
Lane 8/9 Equalization Control Register
RW
RW
RW
RW
Lane 10/11 Equalization Control
Register
DB4–DB7h
DB8–DBBh
DBC–DBFh
EQCTL10_11
EQCTL12_13
EQCTL14_15
07080708h
07080708h
07080708h
RW
RW
RW
Lane 12/13 Equalization Control
Register
Lane 14/15 Equalization Control
Register
DC0–DD7h
DD8–DDBh
RSVD
Reserved
0h
RO
EQCFG
Equalization Configuration Register
F9404400h
RW
132
Datasheet, Volume 2
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