Processor Configuration Registers
2.6.44
RCTL—Root Control Register
This register allows control of PCI Express* Root Complex specific parameters. The
system error control bits in this register determine if corresponding SERRs are
generated when our device detects an error (reported in this device's Device Status
register) or when an error message is received across the link. Reporting of SERR as
controlled by these bits takes precedence over the SERR Enable in the PCI Command
Register.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
0/1/0–2/PCI
BC–BDh
0000h
RO, RW
16 bits
000h
Size:
BIOS Optimal Default
Reset
Value
RST/
PWR
Bit
Access
Description
15:5
RO
0h
Reserved (RSVD)
Reserved for CRS Software Visibility Enable (CSVE)
This bit, when set, enables the Root Port to return Configuration
Request Retry Status (CRS) Completion Status to software.
Root Ports that do not implement this capability must hardwire
this bit to 0b.
4
3
RO
0b
Uncore
Uncore
PME Interrupt Enable (PMEIE)
0 = No interrupts are generated as a result of receiving PME
messages.
1 = Enables interrupt generation upon receipt of a PME message
as reflected in the PME Status bit of the Root Status
Register. A PME interrupt is also generated if the PME Status
bit of the Root Status Register is set when this bit is set from
a cleared state.
RW
0b
If the bit change from 1 to 0 and interrupt is pending than
interrupt is deasserted
System Error on Fatal Error Enable (SEFEE)
Controls the Root Complex's response to fatal errors.
0 = No SERR generated on receipt of fatal error.
1 = Indicates that an SERR should be generated if a fatal error is
reported by any of the devices in the hierarchy associated
with this Root Port, or by the Root Port itself.
2
1
0
RW
RW
RW
0b
0b
0b
Uncore
Uncore
Uncore
System Error on Non-Fatal Uncorrectable Error Enable
(SENFUEE)
Controls the Root Complex's response to non-fatal errors.
0 = No SERR generated on receipt of non-fatal error.
1 = Indicates that an SERR should be generated if a non-fatal
error is reported by any of the devices in the hierarchy
associated with this Root Port, or by the Root Port itself.
System Error on Correctable Error Enable (SECEE)
Controls the Root Complex's response to correctable errors.
0 = No SERR generated on receipt of correctable error.
1 = Indicates that an SERR should be generated if a correctable
error is reported by any of the devices in the hierarchy
associated with this Root Port, or by the Root Port itself.
Datasheet, Volume 2
125
INTEL [ INTEL ]
