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326769-002 参数 Datasheet PDF下载

326769-002图片预览
型号: 326769-002
PDF下载: 下载PDF文件 查看货源
内容描述: 移动第三代英特尔®科雷亚?? ¢处理器家族 [Mobile 3rd Generation Intel® Core™ Processor Family]
分类和应用:
文件页数/大小: 342 页 / 2513 K
品牌: INTEL [ INTEL ]
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Processor Configuration Registers  
2.6.46  
DCAP2—Device Capabilities 2 Register  
B/D/F/Type:  
Address Offset:  
Reset Value:  
Access:  
0/1/0–2/PCI  
C4–C7h  
00000800h  
RO, RW-O  
32 bits  
Size:  
BIOS Optimal Default  
0000000h  
Reset  
Value  
RST/  
PWR  
Bit  
Access  
Description  
31:12  
RO  
0h  
Reserved (RSVD)  
Latency Tolerance and BW reporting Mechanism  
Supported (LTRS)  
A value of 1b indicates support for the optional Latency Tolerance  
& Bandwidth Requirement Reporting (LTBWR) mechanism  
capability.  
Root Ports, Switches and Endpoints are permitted to implement  
this capability. For Switches that implement LTBWR, this bit must  
be set only at the upstream port.  
11  
RO  
1b  
Uncore  
For a multi-Function device, each Function must report the same  
value for this bit.  
For Bridges, Downstream Ports, and components that do not  
implement this capability, this bit must be hardwired to 0b.  
10:6  
5
RO  
0h  
0b  
Reserved (RSVD)  
ARI Forwarding Supported (ARIFS)  
Applicable only to Switch Downstream Ports and Root Ports; must  
be 0b for other Function types. This bit must be set to 1b if a  
Switch Downstream Port or Root Port supports this optional  
capability.  
RW-O  
Uncore  
Uncore  
Completion Time-out Disabled Supported (CTODS)  
A value of 1b indicates support for the Completion Timeout  
Disable mechanism.  
The Completion Timeout Disable mechanism is required for  
Endpoints that issue Requests on their own behalf and PCI  
Express to PCI/PCI-X Bridges that take ownership of Requests  
issued on PCI Express.  
4
RO  
0b  
This mechanism is optional for Root Ports.  
The Root port does not support completion timeout disable.  
Completion Timer Ranges Supported (CTOR)  
Device Function support for the optional Completion Timeout  
programmability mechanism. This mechanism allows system  
software to modify the Completion Timeout value.  
This field is applicable only to Root Ports, Endpoints that issue  
Requests on their own behalf, and PCI Express to PCI/PCI-X  
Bridges that take ownership of Requests issued on PCI Express.  
For all other Functions this field is reserved and must be  
hardwired to 0000b.  
3:0  
RO  
0000b  
Uncore  
0000b = Completion Timeout programming not supported – the  
Function must implement a time-out value in the range 50 μs to  
50 ms.  
Datasheet, Volume 2  
127