欢迎访问ic37.com |
会员登录 免费注册
发布采购

326769-002 参数 Datasheet PDF下载

326769-002图片预览
型号: 326769-002
PDF下载: 下载PDF文件 查看货源
内容描述: 移动第三代英特尔®科雷亚?? ¢处理器家族 [Mobile 3rd Generation Intel® Core™ Processor Family]
分类和应用:
文件页数/大小: 342 页 / 2513 K
品牌: INTEL [ INTEL ]
 浏览型号326769-002的Datasheet PDF文件第127页浏览型号326769-002的Datasheet PDF文件第128页浏览型号326769-002的Datasheet PDF文件第129页浏览型号326769-002的Datasheet PDF文件第130页浏览型号326769-002的Datasheet PDF文件第132页浏览型号326769-002的Datasheet PDF文件第133页浏览型号326769-002的Datasheet PDF文件第134页浏览型号326769-002的Datasheet PDF文件第135页  
Processor Configuration Registers  
2.6.50  
LSTS2—Link Status 2 Register  
B/D/F/Type:  
Address Offset:  
Reset Value:  
Access:  
0/1/0–2/PCI  
D2–D3h  
0000h  
RO-V, RW1C  
16 bits  
000h  
Size:  
BIOS Optimal Default  
Reset  
Value  
RST/  
PWR  
Bit  
Access  
Description  
15:6  
RO  
0h  
Reserved (RSVD)  
Link Equalization Request (LNKEQREQ)  
This bit is set by hardware to request the Link equalization  
process to be performed on the Link. Refer to PCIe Specification,  
Sections 4.2.3 and 4.2.6.4.2 for details.  
5
4
RW1C  
RO-V  
0b  
Uncore  
Uncore  
The Reset Value of this bit is 0b.  
Equalization Phase 3 Successful (EQPH3SUCC)  
When set to 1b, this bit indicates that Phase 3 of the Transmitter  
Equalization procedure has successfully completed. Details of the  
Transmitter Equalization process and when this bit needs to be  
set to 1b is provided in PCIe Specification, Section 4.2.6.4.2.  
0b  
0b  
0b  
0b  
The Reset Value of this bit is 0b.  
Equalization Phase 2 Successful (EQPH2SUCC)  
When set to 1b, this bit indicates that Phase 2 of the Transmitter  
Equalization procedure has successfully completed. Details of the  
Transmitter Equalization process and when this bit needs to be  
set to 1b is provided in PCIe specification Section 4.2.6.4.2.  
3
2
1
RO-V  
RO-V  
RO-V  
Uncore  
Uncore  
Uncore  
The Reset Value of this bit is 0b.  
Equalization Phase 1 Successful (EQPH1SUCC)  
When set to 1b, this bit indicates that Phase 1 of the Transmitter  
Equalization procedure has successfully completed. Details of the  
Transmitter Equalization process and when this bit needs to be  
set to 1b is provided in PCIe specification Section 4.2.6.4.2.  
The Reset Value of this bit is 0b.  
Equalization Complete (EQCOMPLETE)  
When set to 1b, this bit indicates that the Transmitter  
Equalization procedure has completed. Details of the Transmitter  
Equalization process and when this bit needs to be set to 1b is  
provided in PCIe specification Section 4.2.6.4.2.  
The Reset Value of this bit is 0b.  
Current De-emphasis Level (CURDELVL)  
When the Link is operating at 5 GT/s speed, this reflects the level  
of de-emphasis.  
1 = -3.5 dB  
0
RO-V  
0b  
Uncore  
0 = -6 dB  
When the Link is operating at 2.5 GT/s speed, this bit is 0b.  
Datasheet, Volume 2  
131