Processor Configuration Registers
2.6.45
RSTS—Root Status Register
This register provides information about PCI Express* Root Complex specific
parameters.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
0/1/0–2/PCI
C0–C3h
00000000h
RO, RW1C, RO-V
32 bits
Size:
BIOS Optimal Default
0000h
Reset
Value
RST/
PWR
Bit
Access
Description
31:18
RO
0h
Reserved (RSVD)
PME Pending (PMEP)
This bit indicates that another PME is pending when the PME
Status bit is set. When the PME Status bit is cleared by software,
the PME is delivered by hardware by setting the PME Status bit
again and updating the Requestor ID appropriately. The PME
pending bit is cleared by hardware if no more PMEs are pending.
17
RO
0b
Uncore
PME Status (PMES)
This bit indicates that PME was asserted by the requestor ID
indicated in the PME Requestor ID field. Subsequent PMEs are
kept pending until the status register is cleared by writing a 1 to
this field.
An interrupt is asserted if PMEIE is asserted and PMES is
changing from 0 to 1.
An interrupt is deasserted if PMEIE is asserted and PMES is
changing from 1 to 0.
16
RW1C
0b
Uncore
An Assert_PMEGPE is sent upstream if PMEGPEE in PEG Legacy
Control register (PEGLC) is asserted and PMES is changing from 0
to 1.
A Deassert_PMEGPE is sent upstream if PMEGPEE in PEG Legacy
Control register (PEGLC) is asserted and PMES is changing from 1
to 0
An interrupt is deasserted if PMEIE is asserted and PMES is
changing from 1 to 0.
PME Requestor ID (PMERID)
15:0
RO-V
0000h
Uncore
This field indicates the PCI requestor ID of the last PME
requestor.
126
Datasheet, Volume 2
INTEL [ INTEL ]
