®
Intel ICH10 Pin States
Table 3-2.
Power Plane and States for Output and I/O Signals for Configurations (Sheet
4 of 5)
Power
Plane
During
Reset4
Immediately
after Reset4
Signal Name
C3/C4
S1
S3
S4/S5
LINKALERT# /
GPIO60 / JTAGRST#
(Corporate Only)
Suspend
Suspend
High-Z
Input
High-Z
Input
Defined
Defined
Defined
TPM_PP / GPIO57 /
JTAGTCK (Corporate
Only)
Defined
Defined
Defined
SPI_CS[1]#11
Suspend
Suspend
High
High
Defined
Defined
Defined
Defined
Defined
Defined
SMLINK[1:0]
High-Z
High-Z
Miscellaneous Signals
High-Z Low
Intel® High Definition Audio Interface
SPKR11
Core
Defined
Off
Off
HDA
Suspend
HDA_RST#
Low
Low7
Defined
Low
Low
HDA_SDOUT11
HDA_SYNC
HDA
HDA
HDA
Low
Low
Low
Low
Low
Low
Low
Low
Low
Off
Off
Off
Off
Off
Off
HDA_BIT_CLK
UnMultiplexed GPIO Signals
GPIO0 / BMBUSY#
Core
Input
Input
Input
Input
Defined
Defined
Off
Off
Consumer Only:
GPIO8
Suspend
Defined
Defined
GPIO12 /
LAN_PHY_PWR_CTRL
Suspend
Low
Low
Defined
Defined
Defined
GPIO13
GPIO16/DPRSLPVR
GPIO18
Suspend
Core
Input
Low
Input
Low
Defined
Defined
Defined
Defined
Defined
Defined
Defined
Defined
Defined
Defined
Off
Defined
Off
Core
High
Low
See Note 2
High
Off
Off
GPIO2011
Core
Off
Off
GPIO[28:27]
GPIO3311, GPIO32
GPIO34
Suspend
Core
Low
Low
Defined
Off
Defined
Off
High
Low
High
HDA
Low
Off
Off
GPIO4911
Core
High
Input
High
Off
Off
GPIO56
Suspend
Input
Defined
Defined
SPI Interface
Controller
Link
SPI_CS0#
SPI_CS1#11
SPI_MOSI11
SPI_CLK
High
High
Low
Low
High
Defined
Defined
Defined
Running
Defined
Defined
Defined
Defined
Defined
Defined
Defined
Defined
Controller
Link
High
Low
Controller
Link
Controller
Link
Low
Controller Link
Low
Controller
Link
CL_CLK0
Low
Defined10 Defined10 Defined10
86
Datasheet
INTEL [ INTEL ]
