®
Intel ICH10 Pin States
3.3
Power Planes for Input Signals
Table 3-3 shows the power plane associated with each input signal, as well as what
device drives the signal at various times. Valid states include:
High
Low
Static: Will be high or low, but will not change
Driven: Will be high or low, and is allowed to change
Running: For input clocks
The ICH10 suspend well signal states are indeterminate and undefined and may glitch
prior to RSMRST# deassertion. This does not apply to LAN_RST#, SLP_S3#, SLP_S4#,
S4_STATE# and SLP_S5#. These signals are determinate and defined prior to
RSMRST# deassertion.
The ICH10 core well signal states are indeterminate and undefined and may glitch prior
to PWROK assertion. This does not apply to FERR# and THRMTRIP#. These signals are
determinate and defined prior to PWROK assertion.
Table 3-3.
Power Plane for Input Signals for Configurations (Sheet 1 of 3)
Signal Name
Power Well Driver During Reset
DMI
C3/C4
S1
S3
S4/S5
DMI_CLKP,
DMI_CLKN
Core
Core
Clock Generator
(G)MCH
Running
Driven
Off
Off
Off
Off
DMI[3:0]RXP,
DMI[3:0]RXN
PCI Express*
PERp[5:1],
PERn[5:1], PERp6 /
GLAN_RXp, PERn6 /
GLAN_RXn
Core
PCI Express* Device
PCI Bus
Driven
Off
Off
REQ0#,
REQ1# / GPIO501
REQ2# / GPIO521
REQ3# / GPIO541
Core
External Pull-up
Driven
Off
Off
PCICLK
PME#
Core
Suspend
Core
Clock Generator
Internal Pull-up
Running
Driven
High
Off
Driven
Off
Off
Driven
Off
SERR#
PCI Bus Peripherals
LPC Interface
LDRQ0#
LDRQ1# / GPIO231
Core
Core
LPC Devices
LPC Devices
High
High
Off
Off
Off
Off
LAN Connect Interface
LAN Connect
Component
GLAN_CLK
Suspend
Suspend
Driven
Driven
Off
Off
LAN Connect
Component
LAN_RXD[2:0]
Driven
Driven
88
Datasheet
INTEL [ INTEL ]
