®
Intel ICH10 Pin States
Table 3-2.
Power Plane and States for Output and I/O Signals for Configurations (Sheet
3 of 5)
Power
Plane
During
Reset4
Immediately
after Reset4
Signal Name
C3/C4
S1
S3
S4/S5
DPRSTP#
PLTRST#
SLP_M#9
CPU
High
Low
Low
Low
Low
Low
High
High
High
High
Off
Low
Off
Suspend
Suspend
Suspend
Suspend
Suspend
Low
High
High
Defined
Low
Defined
Low
SLP_S3#
High
High
SLP_S4#
High
High
High
Defined
Defined
S4_STATE# / GPIO26
Defined
Defined
Defined
SLP_S5#/ GPIO63
(Corporate Only)
Suspend
Low
High
High
High
Low6
SUS_STAT# /
LPCPD# / GPIO61
(Corporate Only)
Suspend
Low
High
High
Low
Low
SUSCLK
CK_PWRGD
Suspend
Suspend
Suspend
Low
Low
High
Running
High
High
High
Low
Low
STP_PCI# / GPIO15
Defined
Defined
Defined
STP_CPU# / GPIO25
(Corporate Only)
Suspend
High
High
Defined
Defined
Defined
Corporate Only:
DRAMPWROK /
GPIO8
Defined/
Low12
Defined/
Low12
Suspend
Low
Low
Defined
Defined
Processor Interface
DPSLP#
A20M#
CPU
CPU
High
High
High
High
Off
Off
Off
Off
Dependant
on A20GATE
Signal
See Note 1
CPUPWRGD
IGNNE#
INIT#
CPU
CPU
CPU
CPU
CPU
CPU
CPU
Low3
High
See Note 1
High
High
High
High
Low
Low
High
Low
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
High
High
INTR
See Note 5
See Note 5
High
See Note 5
See Note 5
High
NMI
SMI#
STPCLK#
High
High
SMBus Interface
SMBCLK, SMBDATA
MEM_LED / GPIO24
Suspend
High-Z
High-Z
Defined
Defined
Defined
System Management Interface
Suspend
Suspend
Low
Low
Defined
Defined
Defined
Defined
Defined
Defined
CPU_MISSING /
GPIO10 / JTAGTMS
(Corporate Only)
Input
Input
GPIO14 / JTAGTDI
(Corporate Only) /
QST_BMBUSY#
Suspend
Suspend
Input
Input
Defined
Defined
Defined
Defined
Defined
Defined
WOL_EN / GPIO9
High-Z
High-Z
Datasheet
85
INTEL [ INTEL ]
