®
Intel ICH10 Pin States
Table 3-2.
Power Plane and States for Output and I/O Signals for Configurations (Sheet
2 of 5)
Power
Plane
During
Reset4
Immediately
after Reset4
Signal Name
C3/C4
S1
S3
S4/S5
PAR
Core
Suspend
Core
Low
Undefined
High
Defined
High
Off
Low
Off
Off
Low
Off
Off
PCIRST#
PERR#
PLOCK#
STOP#
Low
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
Core
Off
Core
Off
Off
LPC Interface
LAD[3:0] / FWH[3:0]
LFRAME# / FWH[4]
Core
Core
High
High
High
High
High
High
Off
Off
Off
Off
LPCPD# /
SUS_STAT#/ GPIO61
(Corporate Only)
Suspend
Low
High
High
Low
Low
Firmware Hub
INIT3_3V#
Core
High
High
High
Off
Off
LAN Connect Interface
LAN_RSTSYNC
LAN_TXD[2:0]
LAN
LAN
High
Low
Low
Low
Defined
Defined
Defined
Defined
Defined
Defined
Gigabit LAN Connect Interface
GLAN_TXp / PETp6,
GLAN_TXn / PETn6
GLAN
LAN
High
High
High
Defined
Defined
Off
Off
LAN_RSTSYNC
Low
Defined
Defined
SATA Interface
SATA[5:0]TXP,
SATA[5:0]TXN
Core
High-Z
High-Z
Defined
Off
Off
SATALED#11
Core
Core
High-Z
High-Z
High-Z
High-Z
Defined
Defined
Off
Off
Off
Off
SATARBIAS
SATACLKREQ# /
GPIO35
Core
Low
Low
Defined
Off
Off
SCLOCK/GPIO22
SLOAD/GPIO38
Core
Core
Input
Input
Input
Input
Defined
Defined
Off
Off
Off
Off
SDATAOUT[1:0]/
GPIO[48,39]
Core
Input
Input
Defined
Off
Off
Interrupts
PIRQ[A:D]#,
Core
Core
Core
High-Z
Input
High-Z
High-Z
Defined
High-Z
Off
Off
Off
Off
Off
Off
PIRQ[H:E]# /
GPIO[5:2]
Input
SERIRQ
High-Z
High-Z
USB Interface
USB[11:0][P,N]
USBRBIAS
Suspend
Suspend
Low
Low
Defined
Defined
Defined
Defined
Defined
Defined
High-Z
High-Z
Power Management
DPRSLPVR
Core
Low
Low
High
Off
Off
84
Datasheet
INTEL [ INTEL ]
