LPC Interface Bridge Registers (D31:F0)
Bit
Description
Bus Master Status (BM_STS) — R/WC. This bit will not cause a wake event, SCI
or SMI#.
0 = Software clears this bit by writing a 1 to it.
1 = Set by the ICH10 when a bus master requests access to main memory. Bus
master activity is detected by any of the PCI Requests being active, any internal
bus master request being active, or REQ-C2 message received while in C3 or C4
4
state.
NOTE:
1.
If the BM_STS_ZERO_EN bit is set, then this bit will generally report as a 0.
LPC DMA and bus master activity will always set the BM_STS bit, even if the
BM_STS_ZERO_EN bit is set.
3:1
0
Reserved
Timer Overflow Status (TMROF_STS) — R/WC.
0 = The SCI or SMI# handler clears this bit by writing a 1 to the bit location.
1 = This bit gets set any time bit 22 of the 24-bit timer goes high (bits are
numbered from 0 to 23). This will occur every 2.3435 seconds. When the
TMROF_EN bit (PMBASE + 02h, bit 0) is set, then the setting of the TMROF_STS
bit will additionally generate an SCI or SMI# (depending on the SCI_EN).
464
Datasheet
INTEL [ INTEL ]
