LPC Interface Bridge Registers (D31:F0)
13.1.18 PIRQ[n]_ROUT—PIRQ[E,F,G,H] Routing Control Register
(LPC I/F—D31:F0)
Offset Address: PIRQE – 68h, PIRQF – 69h, Attribute:
PIRQG – 6Ah, PIRQH – 6Bh
R/W
Default Value:
Lockable:
80h
No
Size:
8 bit
Core
Power Well:
Bit
Description
Interrupt Routing Enable (IRQEN) — R/W.
0 = The corresponding PIRQ is routed to one of the ISA-compatible interrupts specified
in bits[3:0].
1 = The PIRQ is not routed to the 8259.
7
NOTE: BIOS must program this bit to 0 during POST for any of the PIRQs that are
being used. The value of this bit may subsequently be changed by the OS when
setting up for I/O APIC interrupt delivery mode.
6:4
Reserved
IRQ Routing — R/W. (ISA compatible.)
Value
0000b
0001b
0010b
0011b
0100b
0101b
0110b
0111b
IRQ
Reserved
Reserved
Reserved
IRQ3
Value
1000b
1001b
1010b
1011b
1100b
1101b
1110b
1111b
IRQ
Reserved
IRQ9
IRQ10
IRQ11
IRQ12
Reserved
IRQ14
IRQ15
3:0
IRQ4
IRQ5
IRQ6
IRQ7
Datasheet
397
INTEL [ INTEL ]
