Gigabit LAN Configuration Registers
12.2.3
LDCR2—LAN Device Control Register 2
(Gigabit LAN Memory Mapped Base Address Register)
Address Offset: MBARA + 18h
Attribute:
Size:
R/W
32 bits
Default Value:
01500000h
Bit
Description
31:21 Reserved
LAN PHY Power Down Enable (LPPDE) — R/W. When set, enables the PHY to enter
a low-power state when the LAN controller is at the DMoff / D3 or Dr and no WoL.
20
This bit is loaded from word 13h in the NVM.
LDCR2 Field 1 — R/W. This bit is loaded from word 13h in the NVM.
Reserved
19
19:0
12.2.4
12.2.5
LDCR4—LAN Device Control Register 4
(Gigabit LAN Memory Mapped Base Address Register)
Address Offset: MBARA + 20h
Attribute:
Size:
R/W
32 bits
Default Value:
1000xxxxh
Bit
Description
31:0
BIOS may program this field.
LDR5—LAN Device Control Register 5
(Gigabit LAN Memory Mapped Base Address Register)
Address Offset: MBARA + F00h
Attribute:
Size:
R/W
32 bits
Default Value:
00000000h
Bit
Description
31:6
5
Reserved
LDCR5 Field 1 — R/W. BIOS may set this bit.
4:0
Reserved
12.2.6
LDR1—LAN Device Initialization Register 1
(Gigabit LAN Memory Mapped Base Address Register)
Address Offset: MBARA + 3024h
Attribute:
Size:
R/W
32 bits
Default Value:
60006006h
Bit
Description
31:17 Reserved
16
LDR1 Field 1 — R/W. BIOS must program this field to 1b.
15:0
Reserved
Datasheet
385
INTEL [ INTEL ]
