Gigabit LAN Configuration Registers
12.2
MBARA—Gigabit LAN Base Address A Registers
The internal CSR registers and memories are accessed as direct memory mapped
offsets from the base address register. This block is mapped into memory space, using
the MBARA Base Address register see Section 12.1.10. SW may only access whole
DWord at a time.
Table 12-2. Gigabit LAN Base Address A Registers Address Map (Gigabit LAN— D25:F0)
MBARA+Offset
Mnemonic
Register Name
Default
Type
00–03h
08–0Bh
LDR4
LDR3
LAN Device Initialization 4
LAN Device Initialization 3
LAN Device Control 2
14200100h
00080xxxh
01500000h
1000xxxxh
00000000h
B2B577CCh
600060006h
R/W
RO
18–1Bh
LDCR2
LDCR4
LDCR5
LDR2
R/W
R/W
R/W
R/W
R/W
20–23h
LAN Device Control 4
F00h-F03h
3004–3007h
3024-3027h
LAN Device Control 5
LAN Device Initialization 2
LAN Device Initialization 1
LDR1
12.2.1
LDR4—LAN Device Initialization Register 4
(Gigabit LAN Memory Mapped Base Address Register)
Address Offset: MBARA + 0h
Attribute:
Size:
RO
32 bits
Default Value:
14200100h
Bit
Description
31:25 Reserved
24
LDR4 Field 1 — R/W. BIOS may set this bit to 1.
23:0
Reserved
12.2.2
LDR3—LAN Device Initialization Register 3
(Gigabit LAN Memory Mapped Base Address Register)
Address Offset: MBARA + 8h
Attribute:
Size:
RO
32 bits
Default Value:
00080xxxh
Bit
Description
LDR3 Field 1 — RO. When set, this bit enables the automatic reduction of DMA
frequency. This bit is loaded from word 13h in the NVM.
31
30:0
Reserved
384
Datasheet
INTEL [ INTEL ]
