PCI-to-PCI Bridge Registers (D30:F0)
11.1.10 SMLT—Secondary Master Latency Timer Register
(PCI-PCI—D30:F0)
Offset Address: 1Bh
Default Value: 00h
Attribute:
Size:
R/W
8 bits
This timer controls the amount of time the ICH10 PCI-to-PCI bridge will burst data on
its secondary interface. The counter starts counting down from the assertion of
FRAME#. If the grant is removed, then the expiration of this counter will result in the
de-assertion of FRAME#. If the grant has not been removed, then the ICH10 PCI-to-PCI
bridge may continue ownership of the bus.
Bit
Description
Master Latency Timer Count (MLTC) — R/W. This 5-bit field indicates the number of
PCI clocks, in 8-clock increments, that the ICH10 remains as master of the bus.
7:3
2:0
Reserved
11.1.11 IOBASE_LIMIT—I/O Base and Limit Register
(PCI-PCI—D30:F0)
Offset Address: 1Ch-1Dh
Attribute:
Size:
R/W, RO
16 bits
Default Value:
0000h
Bit
Description
I/O Limit Address Limit bits[15:12] — R/W. I/O Base bits corresponding to address
lines 15:12 for 4-KB alignment. Bits 11:0 are assumed to be padded to FFFh.
15:12
11:8
7:4
I/O Limit Address Capability (IOLC) — RO. This field indicates that the bridge does
not support 32-bit I/O addressing.
I/O Base Address (IOBA) — R/W. I/O Base bits corresponding to address lines 15:12
for 4-KB alignment. Bits 11:0 are assumed to be padded to 000h.
I/O Base Address Capability (IOBC) — RO. This field indicates that the bridge does
not support 32-bit I/O addressing.
3:0
Datasheet
361
INTEL [ INTEL ]
