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319973-003 参数 Datasheet PDF下载

319973-003图片预览
型号: 319973-003
PDF下载: 下载PDF文件 查看货源
内容描述: 英特尔I / O控制器中枢10 [Intel I/O Controller Hub 10]
分类和应用: 控制器
文件页数/大小: 840 页 / 5889 K
品牌: INTEL [ INTEL ]
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PCI-to-PCI Bridge Registers (D30:F0)  
11.1.13 MEMBASE_LIMIT—Memory Base and Limit Register  
(PCI-PCI—D30:F0)  
Offset Address: 20h–23h  
Default Value: 00000000h  
Attribute:  
Size:  
R/W  
32 bits  
This register defines the base and limit, aligned to a 1-MB boundary, of the non-  
prefetchable memory area of the bridge. Accesses that are within the ranges specified  
in this register will be sent to PCI if CMD.MSE is set. Accesses from PCI that are outside  
the ranges specified will be accepted by the bridge if CMD.BME is set.  
Bit  
Description  
Memory Limit (ML) — R/W. These bits are compared with bits 31:20 of the incoming  
31:20 address to determine the upper 1-MB aligned value (exclusive) of the range. The  
incoming address must be less than this value.  
19:16 Reserved  
Memory Base (MB) — R/W. These bits are compared with bits 31:20 of the incoming  
15:4  
3:0  
address to determine the lower 1-MB aligned value (inclusive) of the range. The  
incoming address must be greater than or equal to this value.  
Reserved  
11.1.14 PREF_MEM_BASE_LIMIT—Prefetchable Memory Base  
and Limit Register (PCI-PCI—D30:F0)  
Offset Address: 24h–27h  
Default Value: 00010001h  
Attribute:  
Size:  
R/W, RO  
32-bit  
Defines the base and limit, aligned to a 1-MB boundary, of the prefetchable memory  
area of the bridge. Accesses that are within the ranges specified in this register will be  
sent to PCI if CMD.MSE is set. Accesses from PCI that are outside the ranges specified  
will be accepted by the bridge if CMD.BME is set.  
Bit  
Description  
Prefetchable Memory Limit (PML) R/W. These bits are compared with bits 31:20  
31:20 of the incoming address to determine the upper 1-MB aligned value (exclusive) of the  
range. The incoming address must be less than this value.  
19:16 64-bit Indicator (I64L) RO. Indicates support for 64-bit addressing.  
Prefetchable Memory Base (PMB) R/W. These bits are compared with bits 31:20  
of the incoming address to determine the lower 1-MB aligned value (inclusive) of the  
range. The incoming address must be greater than or equal to this value.  
15:4  
3:0  
64-bit Indicator (I64B) RO. Indicates support for 64-bit addressing.  
Datasheet  
363  
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