PCI-to-PCI Bridge Registers (D30:F0)
11.1.3
PCICMD—PCI Command (PCI-PCI—D30:F0)
Offset Address: 04h–05h
Attribute:
Size:
R/W, RO
16 bits
Default Value:
0000h
Bit
Description
15:11 Reserved
Interrupt Disable (ID) — RO. Hardwired to 0. The PCI bridge has no interrupts to
disable
10
9
Fast Back to Back Enable (FBE) — RO. Hardwired to 0, per the PCI Express* Base
Specification, Revision 1.0a.
SERR# Enable (SERR_EN) — R/W.
0 = Disable.
8
7
6
1 = Enable the ICH10 to generate an NMI (or SMI# if NMI routed to SMI#) when the
D30:F0 SSE bit (offset 06h, bit 14) is set.
Wait Cycle Control (WCC) — RO. Hardwired to 0, per the PCI Express* Base
Specification, Revision 1.0a.
Parity Error Response (PER) — R/W.
0 = The ICH10 ignores parity errors on the PCI bridge.
1 = The ICH10 will set the SSE bit (D30:F0, offset 06h, bit 14) when parity errors are
detected on the PCI bridge.
VGA Palette Snoop (VPS) — RO. Hardwired to 0, per the PCI Express* Base
Specification, Revision 1.0a.
5
4
3
Memory Write and Invalidate Enable (MWE) — RO. Hardwired to 0, per the PCI
Express* Base Specification, Revision 1.0a
Special Cycle Enable (SCE) — RO. Hardwired to 0, per the PCI Express* Base
Specification, Revision 1.0a and the PCI- to-PCI Bridge Specification.
Bus Master Enable (BME) — R/W.
2
1
0 = Disable
1 = Enable. Allows the PCI-to-PCI bridge to accept cycles from PCI.
Memory Space Enable (MSE) — R/W. Controls the response as a target for memory
cycles targeting PCI.
0 = Disable
1 = Enable
I/O Space Enable (IOSE) — R/W. Controls the response as a target for I/O cycles
targeting PCI.
0
0 = Disable
1 = Enable
11.1.4
PSTS—PCI Status Register (PCI-PCI—D30:F0)
Offset Address: 06h–07h
Default Value: 0010h
Attribute:
Size:
R/WC, RO
16 bits
Note:
For the writable bits, software must write a 1 to clear bits that are set. Writing a 0 to
the bit has no effect.
Datasheet
357
INTEL [ INTEL ]
