PCI-to-PCI Bridge Registers (D30:F0)
11.1.15 PMBU32—Prefetchable Memory Base Upper 32 Bits
Register (PCI-PCI—D30:F0)
Offset Address: 28h–2Bh
Attribute:
Size:
R/W
32 bits
Default Value:
00000000h
Bit
Description
Prefetchable Memory Base Upper Portion (PMBU) — R/W. Upper 32-bits of the
prefetchable address base.
31:0
11.1.16 PMLU32—Prefetchable Memory Limit Upper 32 Bits
Register (PCI-PCI—D30:F0)
Offset Address: 2C–2Fh
Attribute:
Size:
R/W
32 bits
Default Value:
00000000h
Bit
Description
Prefetchable Memory Limit Upper Portion (PMLU) — R/W. Upper 32-bits of the
prefetchable address limit.
31:0
11.1.17 CAPP—Capability List Pointer Register (PCI-PCI—D30:F0)
Offset Address: 34h
Attribute:
Size:
RO
8 bits
Default Value:
50h
Bit
Description
Capabilities Pointer (PTR) — RO. This field indicates that the pointer for the first
entry in the capabilities list is at 50h in configuration space.
7:0
11.1.18 INTR—Interrupt Information Register (PCI-PCI—D30:F0)
Offset Address: 3Ch–3Dh
Attribute:
Size:
R/W, RO
16 bits
Default Value:
0000h
Bit
Description
15:8 Interrupt Pin (IPIN) — RO. The PCI bridge does not assert an interrupt.
Interrupt Line (ILINE) — R/W. Software written value to indicate which interrupt line
(vector) the interrupt is connected to. No hardware action is taken on this register.
Since the bridge does not generate an interrupt, BIOS should program this value to FFh
7:0
as per the PCI bridge specification.
364
Datasheet
INTEL [ INTEL ]
