PCI-to-PCI Bridge Registers (D30:F0)
11.1.7
PMLT—Primary Master Latency Timer Register
(PCI-PCI—D30:F0)
Offset Address: 0Dh
Attribute:
Size:
RO
8 bits
Default Value:
00h
Bit
Description
Master Latency Timer Count (MLTC) — RO. Reserved per the PCI Express* Base
Specification, Revision 1.0a.
7:3
2:0
Reserved
11.1.8
11.1.9
HEADTYP—Header Type Register (PCI-PCI—D30:F0)
Offset Address: 0Eh
Attribute:
Size:
RO
8 bits
Default Value:
01h
Bit
Description
7
Multi-Function Device (MFD) — RO. A 0 indicates a single function device
Header Type (HTYPE) — RO. This 7-bit field identifies the header layout of the
configuration space, which is a PCI-to-PCI bridge in this case.
6:0
BNUM—Bus Number Register (PCI-PCI—D30:F0)
Offset Address: 18h-1Ah
Attribute:
Size:
R/W
24 bits
Default Value:
000000h
Bit
Description
Subordinate Bus Number (SBBN) — R/W. This field indicates the highest PCI bus
number below the bridge.
23:16
15:8 Secondary Bus Number (SCBN) — R/W. This field indicates the bus number of PCI.
Primary Bus Number (PBN) — R/W. This field is default to 00h. In a multiple-ICH
system, programmable PBN allows an ICH to be located on any bus. System
configuration software is responsible for initializing these registers to appropriate
7:0
values. PBN is not used by hardware in determining its bus number.
360
Datasheet
INTEL [ INTEL ]
