PCI-to-PCI Bridge Registers (D30:F0)
Bit
Description
Received Target Abort (RTA) — R/WC.
0 = No target abort received.
12
1 = Set when the bridge receives a target abort status from the backbone.
Signaled Target Abort (STA) — R/WC.
0 = No signaled target abort
1 = Set when the bridge generates a completion packet with target abort status on the
backbone.
11
10:9
Reserved.
Data Parity Error Detected (DPD) — R/WC.
0 = Data parity error Not detected.
1 = Set when the bridge receives a completion packet from the backbone from a
8
previous request, and detects a parity error, and CMD.PERE is set (D30:F0:04 bit
6).
7:5
4
Reserved.
Capabilities List (CLIST) — RO. Hardwired to 1. Capability list exist on the PCI
bridge.
Interrupt Status (IS) — RO. Hardwired to 0. The PCI bridge does not generate
interrupts.
3
2:0
Reserved
11.1.5
11.1.6
RID—Revision Identification Register (PCI-PCI—D30:F0)
Offset Address: 08h
Attribute:
Size:
RO
8 bits
Default Value:
See bit description
Bit
Description
Revision ID — RO. Refer to the Intel® I/O Controller Hub (ICH10) Family
Specification Update for the value of the Revision ID Register
7:0
CC—Class Code Register (PCI-PCI—D30:F0)
Offset Address: 09h-0Bh
Attribute:
Size:
RO
24 bits
Default Value:
060401h
Bit
Description
23:16 Base Class Code (BCC) — RO. Hardwired to 06h. Indicates this is a bridge device.
Sub Class Code (SCC) — RO. Hardwired to 04h. Indicates this device is a PCI-to-PCI
bridge.
15:8
Programming Interface (PI) — RO. Hardwired to 01h. Indicates the bridge is
subtractive decode
7:0
Datasheet
359
INTEL [ INTEL ]
