PCI-to-PCI Bridge Registers (D30:F0)
11 PCI-to-PCI Bridge Registers
(D30:F0)
The ICH10 PCI bridge resides in PCI Device 30, Function 0 on bus #0. This implements
the buffering and control logic between PCI and the backbone. The arbitration for the
PCI bus is handled by this PCI device.
11.1
PCI Configuration Registers (D30:F0)
Note:
Address locations that are not shown should be treated as Reserved (see Section 9.2
for details).
.
Table 11-1. PCI Bridge Register Address Map (PCI-PCI—D30:F0) (Sheet 1 of 2)
Offset
Mnemonic
VID
Register Name
Vendor Identification
Default
Type
00h–01h
8086h
RO
See register
description
02h–03h
DID
Device Identification
RO
04h–05h
06h–07h
PCICMD
PSTS
PCI Command
PCI Status
0000h
0010h
R/W, RO
R/WC, RO
See register
description
08h
RID
Revision Identification
RO
09h–0Bh
0Dh
CC
Class Code
060401h
00h
RO
RO
PMLT
Primary Master Latency Timer
Header Type
0Eh
HEADTYP
BNUM
SMLT
01h
RO
18h–1Ah
1Bh
Bus Number
000000h
00h
RO
Secondary Master Latency Timer
I/O Base and Limit
Secondary Status
R/W
1Ch–1Dh IOBASE_LIMIT
0000h
0280h
00000000h
R/W, RO
R/WC, RO
R/W
1Eh–1Fh
20h–23h
SECSTS
MEMBASE_LIMIT
Memory Base and Limit
PREF_MEM_BASE Prefetchable Memory Base and
24h–27h
28h–2Bh
00010001h
00000000h
00000000h
R/W, RO
R/W
_LIMIT
Limit
Prefetchable Memory Upper 32
Bits
PMBU32
Prefetchable Memory Limit Upper
32 Bits
2Ch–2Fh
34h
PMLU32
CAPP
R/W
Capability List Pointer
Interrupt Information
50h
RO
3Ch–3Dh INTR
0000h
R/W, RO
R/WC, RO,
R/W
3Eh–3Fh
BCTRL
Bridge Control
0000h
40h–41h
44h–47h
48h–4Bh
SPDH
DTC
Secondary PCI Device Hiding
Delayed Transaction Control
Bridge Proprietary Status
0000h
R/W, RO
R/W
00000000h
00000000h
BPS
R/WC, RO
Datasheet
355
INTEL [ INTEL ]
