Chipset Configuration Registers
10.1.72 PRSTS—Power and Reset Status (Corporate Only)
Offset Address: 3310–3313h
Attribute:
Size:
RO, R/WC
32-bit
Default Value:
TBDh
Bit
Description
31:16
15
Reserved
Power Management Watchdog Timer-R/WC. This bit is set when the Power
Management watchdog timer causes a global reset.
14:7
6
Reserved
Intel® Management Engine Watchdog Timer Status-R/WC. This bit is set when
the Intel® Management Engine watchdog timer causes a global reset.
Wake On Lan Override Wake Status (WOL_OVR_WK_STS) — R/WC. This bit
gets set when all of the following conditions are met:
•
•
•
Integrated LAN Signals a Power Management Event
The system is not in S0
The “WOL Enable Override” bit is set in configuration space.
5
BIOS can read this status bit to determine this wake source.
Software clears this bit by writing a 1 to it.
4
3
Reserved
ME Host Power Down (ME_HOST_PWRDN) — R/WC.This bit is set when the Intel
ME generates a host reset with power down.
ME Host Reset Warm Status (ME_HRST_WARM_STS) — R/WC. This bit is set
when the Intel Management Engine generates a Host reset without power cycling.
Software clears this bit by writing a 1 to this bit position.
2
1
ME Host Reset Cold Status (ME_HRST_COLD_STS) — R/WC. This bit is set when
the Intel Management Engine generates a Host reset with power cycling. Software
clears this bit by writing a 1 to this bit position.
ME WAKE STATUS (ME_WAKE_STS) — R/WC. This bit is set when the Intel
Management Engine generates a Non-Maskable wake event, and is not affected by
any other enable bit. When this bit is set, the Host Power Management logic wakes to
S0.
0
Datasheet
343
INTEL [ INTEL ]
