Chipset Configuration Registers
10.1.68 OIC—Other Interrupt Control Register (Corporate Only)
Offset Address: 31FE–31FFh
Attribute:
Size:
R/W
16-bit
Default Value:
0000h
Bit
Description
15:10
Reserved
Coprocessor Error Enable (CEN) — R/W.
0 = FERR# will not generate IRQ13 nor IGNNE#.
1 = If FERR# is low, the Intel ICH10 generates IRQ13 internally and holds it until an
I/O port F0h write. It will also drive IGNNE# active.
9
APIC Enable (AEN) — R/W.
0 = The internal IOxAPIC is disabled.
8
1 = Enables the internal IOxAPIC and its address decode.
NOTE: SW should read this register after modifying APIC enable bit prior to access to
the IOxAPIC address range.
APIC Range Select (ASEL) — R/W.These bits define address bits 19:12 for the
IOxAPIC range. The default value of 00h enables compatibility with prior ICH
products as an initial value. This value must not be changed unless the IOxAPIC
Enable bit is cleared.
7:0
NOTE: FEC10000h – FEC3FFFFh is allocated to PCIe when I/OxApic Enable (PAE) bit is set.
10.1.69 OIC—Other Interrupt Control Register (Consumer Only)
Offset Address: 31FF–31FFh
Attribute:
Size:
R/W
8-bit
Default Value:
00h
Bit
Description
APIC Range Select (ASEL) — R/W.These bits define address bits 15:12 for the
IOxAPIC range. The default value of 0h enables compatibility with prior ICH products
as an initial value. This value must not be changed unless the IOxAPIC Enable bit is
cleared.
7:4
3:2
1
Reserved
Coprocessor Error Enable (CEN) — R/W.
0 = FERR# will not generate IRQ13 nor IGNNE#.
1 = If FERR# is low, the Intel® ICH10 generates IRQ13 internally and holds it until an
I/O port F0h write. It will also drive IGNNE# active.
APIC Enable (AEN) — R/W.
0 = The internal IOxAPIC is disabled.
0
1 = Enables the internal IOxAPIC and its address decode.
NOTE: SW should read this register after modifying APIC enable bit prior to access to
the IOxAPIC address range.
Datasheet
341
INTEL [ INTEL ]
